Abstract：In order to meet the application requirements of frequency synthesizer for wireless sensor network (WSN) frontend, a 4.8 GHz LC voltagecontrolled oscillator (VCO) was designed and implemented based on TSMC 0.18 μm RF CMOS process. The core circuit was biased by current, and complementary differential negative resistance LC oscillator structure was adopted with a threebit switch capacitor array. Common source structure was adopted as the output buffer. Circuit design was given, and noise restriction was analyzed in detail. The chip layout was designed in Cadence with 700 μm×900 μm pad. Simulation was completed under 1.8 V supply voltage. Two SSGSS probes and a threepin DC probe were used for chip verification and measurement. The results show that the tuning range of postsimulation can achieve more than 25%, which can perfectly compensate the frequency offset due to process corners. The phase noise of postsimulation is -126.8 dBc/Hz@3 MHz for the carrier of 4.8 GHz. In actual chip detection, the tuning range is 24%, and the phase noise of -121.12 dBc/Hz is obtained at 3 MHz offset with core circuit operating current of only 2 mA.
2011, Vol. 32 
