Abstract： In order to solve the limitations of traditional recognition methods with long time system learning and recognition, and poor readability of learning results, an evolvable hardware (EHW)based road speed limit sign recognition method was proposed. Through the processes of location and feature extraction for the four kinds of normal traffic signs, the preprocessed feature vectors were employed as training and test dataset. The EHWbased recognition system was designed by VHDL and realized on a Xilinx Virtex xcv2000E. In order to improve the system learning speed and recognition accuracy, an incremental evolution strategy and a statistical recognition method were introduced. The performance of the EHW recognition system was analyzed and compared for various experimental settings. The results show that under different outdoor environments the average recognition rate and the recognition time of the proposed evolvable system are 92.31% and 0.12 μs, respectively. The proposed scheme is an efficient tool for road limit sign recognition.
2011, Vol. 32 
